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UltraScale+ Integrated 100G Ethernet Subsystem
Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC), Physical Coding Sublayer (PCS), and IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) Subsystem to enable new emerging optical solutions such as SR4, CWDM4, PSM4, or ER4f for high performance applications.
The Xilinx 100G Ethernet Subsystem provides high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The PCS portion of the IP can be configured in CAUI-10 (10 lanes x 10.3125G), CAUI-4 (4 lanes x 25.78125G) or a dynamically switchable CAUI-10 and CAUI-4 mode with optional built-in RS-FEC.
The Xilinx 100G Ethernet Subsystem provides high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The PCS portion of the IP can be configured in CAUI-10 (10 lanes x 10.3125G), CAUI-4 (4 lanes x 25.78125G) or a dynamically switchable CAUI-10 and CAUI-4 mode with optional built-in RS-FEC.
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