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UltraScale Interlaken
The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect protocol designed to enable the following for use in select UltraScale architectures:
* The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
* The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
* The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
* The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
* The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
* The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
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- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC