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UMC 0.18um 3.3v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run at about 100MHz. By setting different values of DM(4:0) and DN(5:0) according to different REFin frequency, BAKo will be locked at the rising edge of REFin and the output frequency (Cko) will be locked at the multiples of the input frequency.
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