English
You are here:
UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library
UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library
View UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library full description to...
- see the entire UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library datasheet
- get in contact with UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library Supplier
Logic Libraries IP
- Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
- Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)
- Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)
- SMIC 0.13um Low Leakage UHD RVT_x000D_ Logic standard cell library, compatible with E-Flash and EEPROM process.