English
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
You are here:
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.
View UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler. full description to...
- see the entire UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler. datasheet
- get in contact with UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler. Supplier