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UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.
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Memory Compiler IP
- Ultra High-Speed Cache Memory Compiler
- TSMC CLN12FFC Ternary Content Addressable Memory Compiler
- TSMC CLN5FF Ternary Content Addressable Memory Compiler with Column Redundancy
- TSMC CLN7FF Pre-search and Pipeline Ternary Content Addressable Memory Compiler
- Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k