Universal Asynchronous Receiver/Transmitter Core
Features
- Programmable automated RTS and CTS generation
- In automated CTS mode, CTS controls transmitter
- In automated RTS mode, receive FIFO contents and threshold control RTS
- Fully backward compatible with 16450 UARTs
- In the 16450 mode, Hold and Shift registers eliminate the necessity of precise synchronization between the CPU and serial data
- Programmable aud Rate Generator allows division of any input reference clock by 1 to (216 %961) and generates an internal 16x clock
- Standard asynchronous communication bits (Start, Stop, and Parity) added to or deleted from the serial data stream
- Independent receiver clock input
- Fully prioritized interrupt system controls
- Transmit, Receive, Line Status, and Data Set interrupts independently controlled
- Fully programmable serial interface characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit
- Generation and Detection
- 1-, 1 1/2-, or 2-Stop bit generation
- Baud Generation
- False-start bit detection
- Extensive status reporting capabilities
- Line break generation and detection
- Internal diagnostic capabilities:
- Loopback controls for serial link fault isolation
- Break, Parity, Overrun, and Framing error simulation
- Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
- Fully synthesizable RTL Level Verilog core
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UART - Universal Asynchronous Receiver Transmitter IP
- UART : Universal Asynchronous Receiver Transmitter Core
- DO-254 AXI Universal Asynchronous Receiver Transmitter (UART) 16550 1.00a
- Universal Asynchronous Receiver / Transmitter
- Synchronous Universal Asynchronous Receiver/Transmitter
- Universal Asynchronous Receiver Transmitter
- Universal Asynchronous Receiver / Transmitter