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Universal Asynchronous Receiver / Transmitter
The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a serial communication channel.
This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
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UART - 16550 - NS16550 - Universal Asynchronous Receiver / Transmitter IP
- UART : Universal Asynchronous Receiver Transmitter Core
- DO-254 AXI Universal Asynchronous Receiver Transmitter (UART) 16550 1.00a
- High Speed UART IP core - Universal Aysynchronous Receiver / Transmitter
- Universal Asynchronous Receiver / Transmitter
- UART with FIFOs
- Configurable UART with FIFO, software and hardware flow control