Up to 1.25 Gbps DDR LVDS IPs library
• Transmitter LVDS driver (LVDS_TX);
• Receiver LVDS driver (LVDS_RX);
• Bandgap reference block (LVDS_BG);
• Bias blocks (LVDS_BIASRXnX, LVDS_BIASTXnX) for receiver and transmitter with the number of output currents (n = 1, 2, 4, 8, 16, 32)
The bias blocks LVDS_BIASRXnX is intended to generate output currents for LVDS_RX drivers and LVDS_BIASTXnX could generate output currents for LVDS_RX and LVDS_TX drivers both. LVDS_RX cells comprise a voltage comparator with input connected to the 100Ohm termination resistor by EN_RES pin.
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LVDS IP
- Bi-Directional LVDS with LVCMOS
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane