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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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USB 10Gbps Device Controller
Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the FPGA built-in transceiver. It is a one-stop solution for all USB requirements ranging from USB 3.1 to USB 2.0. It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.1 interface with better stability. It provides USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY.
It has been designed to provide simplicity and flexibility along with highest throughput around 8.5Gbps. Avalon/AXI interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
It has been designed to provide simplicity and flexibility along with highest throughput around 8.5Gbps. Avalon/AXI interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
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Block Diagram of the USB 10Gbps Device Controller IP Core
Video Demo of the USB 10Gbps Device Controller IP Core
This video showcase the performance achieved for the eUSB 3.1 Gen 2 Device Controller IP Core on Arria 10 GX development kit.