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Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
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USB 20Gbps Device Controller
Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver. It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0. It supports SuperSpeed+ (SSP x2/x1), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.2 interface with better stability. It provides USB 3.2 backward compatibility with inbuilt transceiver and USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY.
It has been designed to provide simplicity and flexibility along with highest throughput i.e. >16Gbps. Avalon interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
It has been designed to provide simplicity and flexibility along with highest throughput i.e. >16Gbps. Avalon interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
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Block Diagram of the USB 20Gbps Device Controller IP Core
Video Demo of the USB 20Gbps Device Controller IP Core
This video showcases the performance achieved for the USB 20Gbps Device Controller IP Core on Altera Cyclone 10 GX development kit.