USB 3.0 Gen1 / Gen2 Device Controller IP
The USB 3.0 device controller can include an proprietary EP0 processor block for managing all standard requests directed to the control endpoint, minimizing software development overheads. Class and vendor specific requests directed to the control endpoint are routed to the software via the DMA engine, for processing. Optionally, the controller can be provided with no DMA Engine and no buffering. This operates in a cut-through mode, forwarding and receiving USB payloads and managing only the USB protocol. In this case, the customer may implement their own differentiated DMA engine. A simple transmit and receive buffer is also included in this configuration which, accessible by software over the slave register access interface (typically AHB). This option results in very low-footprint hardware which can be used where the software can completely manage the USB traffic including USB transactions sequencing.
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Block Diagram of the USB 3.0 Gen1 / Gen2 Device Controller IP
USB IP IP
- HDCP 2.3 Embedded Security Modules on DisplayPort/USB Type-C
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- Multi-protocol SerDes PMA
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core