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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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USB 3.0 OTG PHY IP, UMC 0.11um HS/AE process
USB3.0 PHY, UMC 0.11um HS/AE Logic process.
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USB3 PHY IP
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- USB 3.0 PHY
- USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process