USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP

The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interface protocols (USB High-speed and Full speed). Supporting additional internal power gating, reference clock control, and PLL control allows for reduced power use. The PHY is particularly useful for a variety of situations under various considerations of power consumption because of the flexibility of the aforementioned low power mode option.

• see the entire USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP datasheet
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