USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 55LL

The combined PHY complies with the Peripheral Component Interconnect Express (PCIe), Serial ATA, USB, USB 3.0, and USB 2.0 interface protocols (USB High-speed and Full speed). Reduced power usage is made possible by supporting extra internal power gating, reference clock control, and PLL control. Because of the versatility of the previously mentioned low power mode option, the PHY is also particularly suitable for a variety of situations under different considerations of power consumption.

• see the entire USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 55LL datasheet
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