USB 3.0 PHY IP, Silicon Proven in TSMC 55LP

For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered. The UTMI, USB 3.0, and USB 2.0 PIPE requirements are met by the PHY (USB SuperSpeed). The USB3.0 PHY IP transceiver is designed to consume little power and take up little space on the chip without compromising speed or data throughput. By providing a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, an integrated self-test module with built-in jitter injection, and a dynamic equalization circuit, the USB3.0 PHY IP delivers total support for high-performance designs. The USB3 MAC layer enables many IP sources to share a PHY interface (PIPE). Internal test monitoring and jitter are eliminated by constant power, built-in Jitter Injection Output, built-in Self-Test, and enabled customization of analogue circuit parameters.

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