USB 3.1 Gen1 / Gen2 Host Controller IP

USB 3.1 Host Controller is compliance with USB3.1 specification, Revision 1.0 and all associated ECN’s, USB specifications Rev 2.0 and all associated ECN’s. USB 3.1 Host controller is architected to optionally include a High Performance DMA Engine based on xHCI Specification. All buffering associated with the DMA Engine are configurable based on latency and performance requirements. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
USB 3.1 Host controller exposes either a AXI or AHB Master Interface for the Datapath and an AHB Slave Interface for Register Access. Optionally, a interoperate proven 3rd Party PCIe-AXI/AHB bridge can be provided for use in standard desktop / server applications. Optionally, the controller can be provided with no xHCI Engine and no buffering and operates in a cut-through mode forwarding and receiving USB payloads and managing only the USB protocol. Customer may in this case implement its own differentiated DMA Engine. Optionally, a simple transmit and receive buffer is included in this configuration which can be accessed by software over the slave register access interface which is typically AHB. This option results in very low footprint hardware which can be used in cases where the software can completely manage the USB traffic – including the sequencing of the USB transactions.

• see the entire USB 3.1 Gen1 / Gen2 Host Controller IP datasheet
• get in contact with USB 3.1 Gen1 / Gen2 Host Controller IP Supplier