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USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
It supports both USB 3.1 Gen1 and Gen2 with this PHY IP. By offering a complete on-chip physical transceiver solution with built-in jitter injection, an integrated self-test module, and protection against Electro Static Discharge (ESD). This USB 3.1 Gen2 PHY IP can be used as a host or device and implements a USB 3.1 Gen2 transceiver. PHY IP supports Gen1 5Gbps data rate as well as USB3.1 Gen2 high speed data rates up to 10Gbps with integrated mixed signal circuit.
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Block Diagram of the USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
USB 3.1 phy IP
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