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USB2.0 OTG PHY in SMIC 40NLL
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design.
The USB2.0 OTG PHY supports the USB2.0 480Mbps protocol and data rate, and is backward compatible with the USB 1.1 1.5Mbps and 15Mbps protocol and data rates.
It has been verified by a number of end products, especially suitable for the internet of things(IoT) applications.
The USB2.0 OTG PHY supports the USB2.0 480Mbps protocol and data rate, and is backward compatible with the USB 1.1 1.5Mbps and 15Mbps protocol and data rates.
It has been verified by a number of end products, especially suitable for the internet of things(IoT) applications.
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USB2.0 IP
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
- USB2.0 Host Transceiver PHY
- USB2.0 OTG PHY supporting UTMI+ level 3 interface - 40LL / 110G / 130G / 130EF
- USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
- Embedded Host Controller 2.0