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USB2.0 PHY
Features
- Support USB HS and FS working mode
- Fully comply with USB2.0 and USB1.1 specification
- Comply with UTMI interface specification
- Embeded Clock and Data Recovery (CDR)
- Crystal-free option available
- Embedded Bit Stuffing and data encoding function
- Embedded Bit Un-Stuffing and decoding function
- SYNC and EOP packet generation and detection
- Programmable 8/16 bits parallel bus width
- Embedded termination resistors
- Do not need any external component
- Built in self-test facility
- Supports USB suspend state and wakeup
- Ultra low power consumption
View USB2.0 PHY full description to...
- see the entire USB2.0 PHY datasheet
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Block Diagram of the USB2.0 PHY IP Core
USB 2.0 PHY IP
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
- USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
- USB 2.0 PHY