V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX

The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a transmitter and receiver are laid out in the V-by-One®HS Standard. This has an available 8-lane PHY and 16-lane PHY for Tx and Rx, and it supports up to 4Gbps/lane. an LVDS Receiver physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS receivers and can handle 1.5Gbps of data flow. There is a 25MHz to 150MHz input clock. The serializer is completely internal and doesn't need any extra parts. The circuit is modularly constructed and desensitized to handle changes. This makes process migration easier and produces a solid design.

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