55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
V-By-One Receiver_8ch
Innosilicon VBO RX IP is composed of physical layer and digital controller. The physical layer contains 8 data lanes and bias circuit. The data lane consists of termination, equalizer and CDR circuit. In each data lane, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The equalizer firstly changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. Then the input signals are reshaped by equalizer for frequency compensation. Finally, the serial stream is recovered by CDR and converted to 10-bit parallel output. The bias circuit generates voltage and current reference.
The digital controller contains 8 data process paths to deal with the recovered video data. Each path consists of 10b/8b decoder, descrambler and 3/4/5-byte unpacker. The recovered video data are finally converted to 40-bit video data, 24-bit control data and timing data.
Innosilicon VBO RX IP offers reliable implementation for VBO interface, which can be integrated in the SOC used in multimedia device.
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