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Scalable UHD H.264 Encoder - Ultra-High Throughput, Full Motion Estimation engine
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VESA Display Stream Compression (DSC) IP Core
Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resolution video technologies. Bitec offer a highly optimized implementation of the DSC 1.2a as a stand-alone component and/or an integrated component to the Bitec DisplayPort 1.4 and HDMI 2.1 IP Cores.
Display Stream Compression offers inter-operable, visually lossless, real-time video compression to satisfy the emerging high bandwidth and high resolution video technologies. Bitec offers a highly optimized implementation of the DSC 1.2a as a stand-alone component and/or integrated component to the Bitec DisplayPort 1.4 and HDMI 2.1 IP Cores.
The DSC encoder or decoder has a rich set of parameterizations to enable an optimal customer implementation. User parameterized number of slices enables targeting of different transport protocols such as MIPI or DisplayPort.
Display Stream Compression offers inter-operable, visually lossless, real-time video compression to satisfy the emerging high bandwidth and high resolution video technologies. Bitec offers a highly optimized implementation of the DSC 1.2a as a stand-alone component and/or integrated component to the Bitec DisplayPort 1.4 and HDMI 2.1 IP Cores.
The DSC encoder or decoder has a rich set of parameterizations to enable an optimal customer implementation. User parameterized number of slices enables targeting of different transport protocols such as MIPI or DisplayPort.
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Block Diagram of the VESA Display Stream Compression (DSC) IP Core
VESA DSC IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs