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VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.
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Block Diagram of the VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
DisplayPort IP
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DisplayPort 2.0 FEC RX
- Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA