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VESA DSC Encoder IP
DSC ENCODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. DSC ENCODER IIP is proven in FPGA environment. The host interface of the DSC ENCODER can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
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vesa dsc IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs