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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process FF/P
Specialty Memory Solutions
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memory compiler IP
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- Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k