MIPI D-PHY DSI RX (Receiver) IP

The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and consists of 3 lanes: 1 Clock lane and 2 data lanes, which makes it suitable for display interface applications (DSI). The High-Speed signals have a low voltage
swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

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