English
You are here:
Virtex-6 FPGA GTH Transceiver Wizard
The LogiCORE™ IP Virtex®-6 GTH Transceiver Wizard automates the task of creating HDL wrappers to configure Xilinx Virtex-6 FPGA GTH on-chip transceivers. The Wizard’s customization GUI allows users to configure one or more GTH high-speed serial transceivers using either pre-defined templates supporting popular industry standards, or from scratch, to support a wide variety of custom protocols.
View Virtex-6 FPGA GTH Transceiver Wizard full description to...
- see the entire Virtex-6 FPGA GTH Transceiver Wizard datasheet
- get in contact with Virtex-6 FPGA GTH Transceiver Wizard Supplier
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC