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Virtex-6 Integrated Block for PCI Express (PCIe)
Xilinx provides a Virtex-6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex-6 FPGA Integrated Block for PCIe FPGA and includes additional logic to create a complete solution for PCIe. This Xilinx Block Wrapper for PCIe simplifies the design process and reduces time-to-market. Many easy-to-use features and optimal configuration for Endpoint and Root Port applications are available at no additional cost. This solution can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other Xilinx connectivity solutions helps customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces. All registered ISE users can request a license file by first registering for the wrapper (“Register”)
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC