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DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - 40nm LL
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Warping Engine IP block for image transformation, HUDs and fish-eye correction
TES Warping Engine is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory-to-memory or memory-to-stream. Applications are for example pre-warping for projection on head-up displays or fisheye-correction of camera images.
The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).
The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).
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