Wrapper IP building blocks for ES1 IP

Features

• GMII 2 RGMII/SGMII adapter: PHYs and SFPs; built-in MDIO / I2C controller for -PHY
• Memory protection for high integrity/availability systems: SEC/DED protection of TTE End System Core Memories; built-in self-test of memories; memory scrubbing
• TTE end system core streaming adapter: Allows interfacing TTE-ES core from user application via packet interface (AXI-S)
• TTE end system core DMA engine: Support for high latency buses like PCIe while reaching line (1Gbps) throughputs. Customization for any PCIe HARD IP is possible; variant of DMA for SoC use (AMBA interfacing)