NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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x4 - High Performance 8-bit RISC Microcontroller
The DRPIC1655X soft core is software-compatible with the industry standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories), with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The advantage of this architecture, is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data, from the data memory. The DRPIC1655X architecture is 4 times faster compared to standard architecture. Most instructions are executed within 1 system clock period, except the instructions, which operate directly on PC (GOTO, CALL, RETURN) program counter. This situation requires the pipeline to be cleared and subsequently refilled. This operation takes additional one clock cycle.
The DRPIC1655X Microcontroller perfectly fits in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC165X is delivered with fully automated testbench, complete set of tests and DoCD TM on-chip hardware debugger, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's PIC Core, has built-in support for the DCD Hardware Debug System called DoCD . It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.
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