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XTS-AES IEEE P1619 Core Families
XTS2 and XTS3 (formerly known as XEX2 and XEX3) implement the NIST standard AES cipher in the XEX/XTS mode for encryption and decryption. The XTS3 family of cores covers a wide range of area / throughput combinations using both 256 and 128-bit keys, allowing the designer to choose the smallest core that satisfies the desired clock/throughput requirements. XTS2 is similar to XTS3, but supports only 128-bit keys. Each core contains the base AES core AES1 and is available for immediate licensing.
The design is fully synchronous and available in both source and netlist form.
The design is fully synchronous and available in both source and netlist form.
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Block Diagram of the XTS-AES IEEE P1619 Core Families IP Core
