AndesCore™ AX25 is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is tailored for high-performance embedded applications that needs ...

AndesCore™ NX25F is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is tailored for high-performance embedded applications that needs ...

The 64-bit AX27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instructions, "C" 16-bit compression instructions, "P" Packed-SIMD/DSP ...

The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the IMAFD standard instructions, “C” 16-bit compression instructions, ...

The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” ...

The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the IMAFD standard instructions, “C” 16-bit compression instructions, ...

The DRV64IMZicsr is a 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support. As a part of the DRVX Core Family this unique CPU offers: * five-stage pipeline, * Harvard ...

The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based ...

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AndesCore™ AX25MP 64-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard 'IMAC-FD' extensions, Andes contributed DSP/SIMD 'P' extension (draft), user-level ...

64-bit Core ; Ready for the most demanding workloads, Atrevido supports large memory capacities with its 64-bit native data path. ; With its complete MMU support, Atrevido is also Linux-ready, ...

SiFive’s E51 Coreplex is a 64-bit embedded processor, fully compliant with the RISC-V ISA. An extremely small-footprint, low-power design makes the E51 Coreplex ideal for devices that require ...

C910 utilizes a 12-stage superscalar pipeline, is compatible with RISC-V architecture, and is enhanced for arithmetic operations, memory access and multi-core synchronization. It also has a ...

64-bit Core ; Ready for the most demanding workloads, Avispado supports large memory capacities with its 64-bit native data path. ; With its complete MMU support, Avispado is also Linux-ready, ...

The S2 Series is a 64-bit microcontroller highly-optimized for area, efficient performance, and simplified integration into 64-bit SoCs. The S2 core has the same efficient 2-stage or 3-stage ...

AndesCore™ A25 is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-MHz performance and operating at high ...

AndesCore™ N25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-MHz performance and operating at high ...

AndesCore™ D25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-MHz performance and operating at high ...

The 32-bit A27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instructions, "C" 16-bit compression instructions, "P" Packed-SIMD/DSP instructions, ...

The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, and “N” ...

The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” ...

AndesCore™ AX45MP 64-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMAC-FD)” extensions, “C” 16-bit ...

AndesCore™ N25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-MHz performance and operating at high ...

AndesCore™ AX45MPV 64-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMA-FD)”, ...

AndesCore™ D25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications. Approved based on the functional safety assignments of a Safety ...

The EP423 64-bit PCI-X host bridge core is optimized to operate in both PCI mode and PCI-X mode. The user interface is a highly efficient and flexible user interface which provides for easy ...

AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G ...

The W65C816i1M16SA Microcontrollers have interfaces for connected Things for sensing, processing, communicating and actuating (SPCA). The microcontrollers are described with the Verilog HDL ...

The SiFive Intelligence X280 is a multi-core capable RISC-V processor with vector extensions and SiFive Intelligence Extensions and is optimized for AI/ML compute at the edge. In addition ...

The SiFive Performance™ P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GBC ISA. The Performance P500 scales up to ...

The latest generation SiFive Performance™ P600-Series processors are the highest performance commercially licensable RISC-V processors. The P670 vector application processor features a ...

The SiFive Performance™ P400-Series application processors are SiFive’s first efficiency-focused Out-of-Order processors. The P400-series is derived from the successful and mature P500-Series, ...

The highest performance RISC-V core is ideal for consumer applications or used in conjunction with a vector processor in the datacenter. The P870 sets an impressive, new RISC-V performance bar ...

The EIP-96 is an Inline Cryptographic Accelerator designed to accelerate and offload the very CPU intensive IPsec, MACsec, SRTP, SSL, TLS and DTLS protocol operations. The In-line Multi-Protocol ...

Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth between the camera and the application processor. ...

The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running either on operating systems or as bare metal. The N13 is designed ...

Chevin Technology’s TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. Chevin Technology’s TCP/IP offloads the TCP protocol ...

The Veriest Register Indirect RAM Access Design IP provides a bridge between the embedded AMBA AHB bus and a configurable number of embedded SRAM devices for test, initialization and other low ...

The SDIO/SD Memory/MMC Host Controller IP Core is a host controller for SD memory card, SDIO and MMC interface. The core connects the host CPU of the system to the SD card socket. SD memory ...

Bring the best-in-class network connectivity to your hardware design with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. ...

The world’s most reliable and mature full hardware UDP/IP and MAC IP Cores. Bring the best-in-class network connectivity to your hardware code and algorithms with Enyx rock-solid and ...