Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD process technologies with no additional masks ...

The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications such as digital cameras, networking ...

Certus provides full LVDS RX & TX IOs in GlobalFoundries and other foundry technologies. The Certus LVDS solutions are ANSI/TIA/EIA-644-A compliant and are capable of data rates of up to 1.5Mbps. ...

The L6GAD10B001M is an 8-channel, 10-bit analog-to-digital converter (ADC), which consists of a successive approximation register(SAR), a capacitor-based ADC, and an inherent sample-and-hold ...

The L6GAD12B001M IP is a successive– approximation-register (SAR) type analog-to-digital converter (ADC), which consists of an 8-channel input MUX, a digital-to-analog converter (DAC), ...

Key attributes of the GlobalFoundries 65nm IO library are dual selectable drive strengths and independent input & output enable / disable. The GPIO cell can be configured as input, output or ...

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 ...

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 ...

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 ...

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable for PC and consumer electronics applications ...

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable for PC and consumer electronics applications ...

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable for PC and consumer electronics applications ...

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance ...

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance ...

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance ...

The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication factors up to 8192, allowing the PLL to ...

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...