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MIPI D-PHY Tx 4 Lanes on TSMC 7FF18 for Automotive

MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC

• Dual mode PHY Supports MIPI Alliance Specification D-PHY v3.5 & C-PHY v2.1
• Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
• Consists of 3 Data lanes in C-PHY mode

PCIe 5.0 PHY for TSMC N3P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

28G Ethernet PHY IP for TSMC N7

• Supports 1.25 to 32 Gbps data-rate
• Supports PCI Express 5.0, 1G to 400G Ethernet, CCIX, CXL, and SATA protocols

Single port SRAM Compiler - low power retention mode

• Ultra-Low Leakage
• Bit Cell
• Ultra Low Power Standby

Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)

• Fully integrated multi-protocol turnkey platform in TSMC 12nm FFC+ for integration into Smart Edge AIoT SoCs

13.56MHz NFC Transceiver IP

20mA and 500mA LDO voltage regulators (output voltage 2.5V)

TSMC ONFI 5.1 3,600MT/s PHY, 7nm, 12nm and 28nm

TSMC MIPI D-PHY Tx 2.5G and MIPI D-PHY Rx 2.5G (Automotive Interface IP)

HBM3 PHY on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard HBM3 DRAMs
• Data rates up to 9600 Mbps

0.6V/10uA, 20uA Bandgap and V2I converter (Voltage to current)

• TSMC MSRF CMOS 55nm
• Dual output reference voltage without trimming 0.6V±3.4%
• Buffered output