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Synopsys 28G Ethernet PHY IP for TSMC N7

Single port SRAM Compiler - low power retention mode

• Ultra-Low Leakage
• Bit Cell
• Ultra Low Power Standby

13.56MHz NFC Transceiver IP

20mA and 500mA LDO voltage regulators (output voltage 2.5V)

TSMC ONFI 5.1 3,600MT/s PHY, 7nm, 12nm and 28nm

TSMC MIPI D-PHY Tx 2.5G and MIPI D-PHY Rx 2.5G (Automotive Interface IP)

HBM3 PHY on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard HBM3 DRAMs
• Data rates up to 9600 Mbps

0.6V/10uA, 20uA Bandgap and V2I converter (Voltage to current)

• TSMC MSRF CMOS 55nm
• Dual output reference voltage without trimming 0.6V±3.4%
• Buffered output

Scalable, On-Die Voltage Regulation for High Current Applications

• Enables per-core DVFS
• Localized IR drop mitigation
• Unlocks virtual power islands

PCIe 6.0 PHY for TSMC N3P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization
• Supports PCIe Lane Margining at Receiver

MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP

• Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
• Consists of 1 Clock lane and 2 Data lanes in D-PHY mode
• Consists of 2 Data Trio in C-PHY mode

Low Dropout (LDO) Capless Regulator

• Input voltage of 1.2V
• Output voltage of 0.84V to 0.93V
• Up to 300mA output current