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Low Dropout (LDO) Capless Regulator

PVT - Process, Voltage, and Temperature Monitor with Interrupt 7nm/6nm

• ± 4C temperature accuracy without trim
• ± 1C temperature accuracy after single room temperature trim
• Voltage monitor supports both single-ended and differential inputs, with 4:1 input mux

40 mA LDO voltage regulator (3.3/5.0V to 1.8V)

• TSMC 180nm technology
• 1.8V output voltage
• Output voltage trimming

Synopsys 224G Ethernet PHY IP for TSMC N3P

PCIe - PCI Express Controller

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL core
• Test Bench. (Environment Variable : Verilog)
• Methodologies - based Test Bench : UVM

7.5 Gbps DDR CML IPs library

• TSMC 40nm LP process
• 2.5V IO voltage supply
• 1.1V core voltage supply

PCIe 6.0 PHY IP for TSMC N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization

uLDO on TSMC 28nm

uLDO on TSMC 130nm

General-purpose LDO on TSMC 28nm

General-purpose LDO on TSMC 130nm

DC/DC on TSMC 28nm