Search IP on TSMC

0.6V/10uA, 20uA Bandgap and V2I converter (Voltage to current)

Scalable, On-Die Voltage Regulation for High Current Applications

Synopsys PCIe 6.0 PHY IP for TSMC N3P

MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP

• Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
• Consists of 1 Clock lane and 2 Data lanes in D-PHY mode
• Consists of 2 Data Trio in C-PHY mode

Low Dropout (LDO) Capless Regulator

PVT - Process, Voltage, and Temperature Monitor with Interrupt 7nm/6nm

• ± 4C temperature accuracy without trim
• ± 1C temperature accuracy after single room temperature trim
• Voltage monitor supports both single-ended and differential inputs, with 4:1 input mux

40 mA LDO voltage regulator (3.3/5.0V to 1.8V)

• TSMC 180nm technology
• 1.8V output voltage
• Output voltage trimming

224G Ethernet PHY IP for TSMC N3P

• Supports full-duplex 1.25 to 224Gbps data rates
• Enables 200G, 400G, 800G, and 1.6T Ethernet
• Ethernet interconnects for wired network infrastructure

PCIe - PCI Express Controller

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL core
• Test Bench. (Environment Variable : Verilog)
• Methodologies - based Test Bench : UVM

7.5 Gbps DDR CML IPs library

• TSMC 40nm LP process
• 2.5V IO voltage supply
• 1.1V core voltage supply

PCIe 6.0 PHY IP for TSMC N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization

uLDO on TSMC 28nm