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New Silicon IP
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TSMC 22nm ULL Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO and 1.8V Analog Cell
- Typical leakage <1nA
- Worst case leakage <80nA
- 150MHz low-leakage GPIO
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PCIe 5.0 PHY for TSMC N7
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
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MIPI D-PHY Tx 4 Lanes on TSMC 7FF18 for Automotive
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
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