TSMC centauro II data IP core / Semiconductor IP / Silicon IP

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TSMC Centauro II data IP Listing

Serial ATA (SATA) I/II PHY IP CORE

MPEG-1/2 – Layer I/II Audio Decoder

I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)

I2C Master / Slave Controller w/FIFO (APB Bus)

I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)

I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)

256x1 Bits OTP (One-Time Programmable) IP, TSM- 0.18μm 1.8V/3.3V Mixed-Signal, General Purpose Process

SD 4.1 UHS-II PHY for TSMC 12nm FF

MIPI M-PHY Compliant (HS-G2) IP

MPEG-1/2 + AAC Audio Decoder

AAC-LC Audio Decoder

802.11 A/B/G/N Direct Conversion Transceiver

SATA 6G PHY

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