RISC-V Compliant Platform Level Interrupt Controller
High Bandwidth Out-of-Order RISC-V CPU IP Core
LINFlexD Controller
Multi Channel FIR Filter
RaiderChip unveils its fully Hardware-Based Generative AI Accelerator: The GenAI NPU
Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
SoC design: What's next for NoCs?
How to Save Time and Improve Communication Between Semiconductor Design and Verification Engineers
Accelerating RISC-V development with Tessent UltraSight-V
Revolutionizing Power Efficiency in PCIe 6.x: L0p and Flit Mode in Action
AMBA LTI Verification IP for Arm System MMU
UCIe for 1.6T Interconnects in Next-Gen I/O Chiplets for AI data centers
Page: 1 2 3 4 5 6 7 8 9 10
© 2024 Design And Reuse
All Rights Reserved.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.
Suppliers, list your IPs for free.
English
