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UltraScale Devices Integrated 100G Ethernet IP Demo
See a demonstration of the integrated 100G Ethernet MAC and CAUI-4 IP available on UltraScale devices. This IP offers savings of up to 80K LUTs and 90% power over a soft implementation and simplifies your design process and time to market by providing proven functionality.
Posted on Wednesday Jun. 11, 2014
Xilinx Channel
Industry's first Gen3 x 16 PCIe solution built into a programmable device
2:30
Zynq UltraScale+ DDR4 Memory Interfaces at 2667Mbps
3:06
DAVE Embedded Systems: Matrix multiply HLS IP with DAVE Bora kit
2:15
Zynq UltraScale+ MPSoC
2:14
16nm UltraScale+ Family
3:15
Using Advanced Encryption Standard Keys with the Battery-Backed (BBR) RAM
8:10
Integrated Interlaken operating at 150 Gb/s in UltraScale FPGAs
3:43
Low Latency 25G/50G Ethernet MAC Connectivity Solution
0:30
Using Multiple Clock Domains in Vivado IP Integrator
6:52
Industry's first Gen3 x 16 PCIe solution built into a programmable device2:30
Zynq UltraScale+ DDR4 Memory Interfaces at 2667Mbps3:06
DAVE Embedded Systems: Matrix multiply HLS IP with DAVE Bora kit2:15
Zynq UltraScale+ MPSoC2:14
16nm UltraScale+ Family 3:15
Using Advanced Encryption Standard Keys with the Battery-Backed (BBR) RAM 8:10
Integrated Interlaken operating at 150 Gb/s in UltraScale FPGAs 3:43
Low Latency 25G/50G Ethernet MAC Connectivity Solution 0:30
Using Multiple Clock Domains in Vivado IP Integrator 6:52