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Key Advantages of Synopsys Memory VIP Architecture
Following on his recent talk about why Synopsys chose a SystemVerilog Architecture for interface VIP, here Synopsys R&D Director Bernie DeLay talks about how a similar architecture based on SystemVerilog for Memory VIP brings some key advantages for verifying the memory interfaces in your SoC design and memory controller IP
Posted on Friday Feb. 06, 2015
Synopsys Channel
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What is USB4? USB, PCIe, and DisplayPort with a Single Type-C Connector2:12
Synopsys at IP SoC Santa Clara 20193:37
IP That Drives Intelligence4:22
Congratulations D&R - Aart de Geus, Synopsys Inc. 9:13
IP Solutions for Securing IoT Devices1:52
DesignWare IP for Embedded Vision, Automotive, FinFET SoCs and more4:30
Keysight Tests Synopsys DesignWare USB 3.1 IP for Compliance3:30
What Designers Need to Know About the PCI Express 4.0 Draft 0.7 Specification4:44
What is an Embedded Vision Processor?4:27
Introduction to Embedded Vision3:05