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Application-Optimized DDR PHYs
Kishore Kasamsetty takes a closer look at how designers continue to get more out of memory subsystems. The traditional one-size-fits-all DDR PHY no longer works. Increasingly, DDR PHYs need to be configured such that they can support unique requirements for a particular application space. This video outlines application-specific DDR PHY from Cadence that offer benefits of optimized power, performance, and area while addressing unique requirements of a targeted application space.
Posted on Wednesday Aug. 31, 2016
Cadence Channel
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Cadence PCIe 4.0 Receiver JTOL Test1:43
Verification with Emerging Memory Models4:12
An Introduction to Palladium Cloud2:04
xSPI Standard Explained3:42
The Storage Combo PHY IP - Nirvana!2:41
What is Happening at the USB IF Standards Meetings?4:03
Cloud-Hosted Design Solution - a Full-Service Cloud Offering2:37
The Reason Why the Vision Q7 DSP Should be in Your Vision and AI SoC5:47
Passport Partners Program Expands Customer Cloud Deployment Options4:36
Cadence Cloud - Fast, Painless, Proven Solutions for Cloud-Based Design7:08