Training DIMMs to 3200 Mbps with DesignWare DDR4/3 PHY IP
See how the Synopsys DDR4/3 PHY IP can program and train a wide variety of UDIMMs, RDIMMs, LRDIMMs and 3DS-DIMMs with excellent signal integrity. You’ll also see the results from a shared AC system and when reflection is introduced to the system.
Posted on Wednesday Jan. 18, 2017
2:12 Synopsys at IP SoC Santa Clara 2019
3:37 IP That Drives Intelligence
4:22 Congratulations D&R - Aart de Geus, Synopsys Inc.
9:13 IP Solutions for Securing IoT Devices
1:52 DesignWare IP for Embedded Vision, Automotive, FinFET SoCs and more
4:30 Keysight Tests Synopsys DesignWare USB 3.1 IP for Compliance
3:30 What Designers Need to Know About the PCI Express 4.0 Draft 0.7 Specification
4:44 What is an Embedded Vision Processor?
4:27 Introduction to Embedded Vision
3:05