NVM OTP in TSMC (180nm, 152nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 22nm, 16nm, 12nm, N7, N6, N5, N4P)
100G OTN Transponder with AES
Scalable UHD H.264 Encoder - Ultra-High Throughput, Full Motion Estimation engine
Display Stream Compression (DSC 1.2) Encoder
Weebit Nano licenses its ReRAM technology to onsemi
Ceva Unveils Ceva-Waves Links200 - A Breakthrough Multi-Protocol Wireless Connectivity Platform IP Featuring Next generation Bluetooth High Data Throughput (HDT) and IEEE 802.15.4
GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services
Quantum Readiness Considerations for Suppliers and Manufacturers
A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
The Fall-Out From Arm vs Qualcomm
How PCIe® Technology is Connecting Disaggregated Systems for Generative AI
From Concept to Reality: Understanding the Cadence Analog IC Design Flow
Gerd Teepe, Director of Marketing for Europe of Globalfoundries Inc. IP SoC 2017 Grenoble December 6th-7th, 2017 Organized by Design and Reuse (D&R)
Posted on Wednesday Dec. 13, 2017
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