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ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
LPDDR4X DRAM: Performance and Power Efficiency Improvements Over LPDDR4
Kishore Kasamsetty will help you learn more about how LPDDR4X can cut down a significant amount of DRAM and SoC PHY power with the use of a 0.6V VDDQ signaling level. LPDDR4X is also available in the highest performance timing bins- 4266 Mbps. Silicon proven LPDDR4X IP in many popular nodes is available from cadence making it ideal for applications requiring high bandwidth with low power.
Posted on Wednesday Jan. 31, 2018
Cadence Channel
Cadence PCIe 4.0 Receiver JTOL Test
1:43
Verification with Emerging Memory Models
4:12
An Introduction to Palladium Cloud
2:04
xSPI Standard Explained
3:42
The Storage Combo PHY IP - Nirvana!
2:41
What is Happening at the USB IF Standards Meetings?
4:03
Cloud-Hosted Design Solution - a Full-Service Cloud Offering
2:37
The Reason Why the Vision Q7 DSP Should be in Your Vision and AI SoC
5:47
Passport Partners Program Expands Customer Cloud Deployment Options
4:36
Cadence Cloud - Fast, Painless, Proven Solutions for Cloud-Based Design
7:08
Cadence PCIe 4.0 Receiver JTOL Test1:43
Verification with Emerging Memory Models4:12
An Introduction to Palladium Cloud2:04
xSPI Standard Explained3:42
The Storage Combo PHY IP - Nirvana!2:41
What is Happening at the USB IF Standards Meetings?4:03
Cloud-Hosted Design Solution - a Full-Service Cloud Offering2:37
The Reason Why the Vision Q7 DSP Should be in Your Vision and AI SoC5:47
Passport Partners Program Expands Customer Cloud Deployment Options4:36
Cadence Cloud - Fast, Painless, Proven Solutions for Cloud-Based Design7:08