English
Test, exercize and debug your PCIe add-in cards with Inspector
Discover how Inspector can be used all along the hardware validation cycle.
From the bring-up phase when Inspector is used for sanity check of the add-in card to the bring-up stage, when Inspector is used for in-depth device testing.
This includes tuning Equalization settings, testing low power capabilities, and performing directed and random stress tests of the PCIe link and interface.
Posted on Wednesday Jun. 26, 2019
PLDA Channel
Demonstration of a CXL Interconnect on a FPGA-based design
6:03
Learn how to configure a PCIe IP with an AXI interconnect
4:44
Discover how to configure XpressRICH IP
5:09
DMA for complex System-on-chip in AI, Automotive and IoT
3:51
DMA for complex System-on-chip in AI, Automotive and IoT
3:51
PCIe Debugging tutorials (Ep1) : 4 common hardware problems
2:24
PCIe solutions for FPGA and ASIC designs
2:11
PLDA Announces PCIe Gen 4 & PCIe Multiport Embedded Switch IP
3:20
PLDA's PCI Express 4.0
1:36
Demonstration of a CXL Interconnect on a FPGA-based design6:03
Learn how to configure a PCIe IP with an AXI interconnect4:44
Discover how to configure XpressRICH IP5:09
DMA for complex System-on-chip in AI, Automotive and IoT3:51
DMA for complex System-on-chip in AI, Automotive and IoT3:51
PCIe Debugging tutorials (Ep1) : 4 common hardware problems 2:24
PCIe solutions for FPGA and ASIC designs2:11
PLDA Announces PCIe Gen 4 & PCIe Multiport Embedded Switch IP3:20
PLDA's PCI Express 4.0 1:36