32-Bit SPARC V8 Processor
ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
Tensilica Vision Q8 DSP
MIPI M-PHY G4 Type 1 1Tx1RX in TSMC (16nm, 12nm, N5)
InPsytech Joins Intel Foundry Accelerator IP Alliance to Boost HPC, AI, And Automotive Applications
Intel's New CEO Called "Strong Choice" to Respin Company
GUC Announces Successful Launch of Industry's First 32G UCIe Silicon on TSMC 3nm and CoWoS Technology
Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Why RISC-V is a viable option for safety-critical applications
RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip Designers
Rambus CryptoManager Root of Trust Solutions Tailor Security Capabilities to Specific Customer Needs with New Three-Tier Architecture
Arm Kleidi Arrives in Automotive Markets to Accelerate Performance for AI-based Applications
Jacek Duda describes three storage protocols and announces that you only need one PHY IP to support xSPI, ONFI 4.x and SD standards!
Posted on Wednesday Jul. 24, 2019
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