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Demonstration of a CXL Interconnect on a FPGA-based design
In this video, we demonstrate the PLDA XpressLINK Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel’s Pre-Production Xeon CPU as a host, connected to an FPGA board, instantiating PLDA’s CXL Controller and CXL.mem test design.
Posted on Thursday Jul. 08, 2021
PLDA Channel
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